Share
High-Level Verification: Methods and Tools for Verification of System-Level Designs (in English)
Rajesh K. Gupta
(Author)
·
Sudipta Kundu
(Author)
·
Sorin Lerner
(Author)
·
Springer
· Paperback
High-Level Verification: Methods and Tools for Verification of System-Level Designs (in English) - Kundu, Sudipta ; Lerner, Sorin ; Gupta, Rajesh K.
$ 104.20
$ 109.99
You save: $ 5.79
Choose the list to add your product or create one New List
✓ Product added successfully to the Wishlist.
Go to My WishlistsIt will be shipped from our warehouse between
Monday, July 01 and
Tuesday, July 02.
You will receive it anywhere in United States between 1 and 3 business days after shipment.
Synopsis "High-Level Verification: Methods and Tools for Verification of System-Level Designs (in English)"
Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
All books in our catalog are Original.
The book is written in English.
The binding of this edition is Paperback.
✓ Producto agregado correctamente al carro, Ir a Pagar.
